`include "ysyx_23060189_cpu.svh"

module ysyx_23060189_PC (
  input  clk,
  input  rst,
  input  wire [`ysyx_23060189_PcSelBus]   PC_sel,
  input  wire [`ysyx_23060189_DataBus]    Alu_out,
  input  wire                             br_taken,
  input  wire [`ysyx_23060189_DataBus]    csr_out,
  input  wire                             wen,
  output wire [`ysyx_23060189_AddrBus]    pc_out,
  output wire [`ysyx_23060189_AddrBus]    pc_4
);

  wire [`ysyx_23060189_AddrBus] pc_in;

  assign pc_4 = pc_out + 4;

  MuxKey #(6, 1 + `ysyx_23060189_PC_SEL_W, `ysyx_23060189_ADDR_W) Mux (pc_in, {br_taken, PC_sel}, {
    {1'b1, `ysyx_23060189_PC_4},   Alu_out,
    {1'b1, `ysyx_23060189_PC_ALU}, Alu_out,
    {1'b1, `ysyx_23060189_PC_CSR}, Alu_out,
    {1'b0, `ysyx_23060189_PC_4},   pc_4,
    {1'b0, `ysyx_23060189_PC_ALU}, Alu_out,
    {1'b0, `ysyx_23060189_PC_CSR}, csr_out
  });

  Reg #(`ysyx_23060189_ADDR_W, `ysyx_23060189_RESET_VAL) pc (
    .clk(clk),
    .rst(rst),
    .din(pc_in),
    .dout(pc_out),
    .wen(wen)
  );
endmodule
